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femtoclock? crystal-to-lvcmos/lvttl frequency synthesizer ics840004-01 idt? / ics? lvcmos/lvttl frequency synthesizer 1 ics840004ag-01 rev. b october 31, 2008 general description the ics840004-01 is a 4 output lvcmos/lvttl synthesizer optimized to generate ethernet reference clock frequencies and is a member of the hiperclocks tm family of high performance clock solutions from idt. using a 25mhz, 18pf parallel resonant crystal, the following frequencies can be generated based on the 2 frequency select pins (f_sel1:0): 156.25mhz, 125mhz, and 62.5mhz. the ics840004-01 uses idt?s 3 rd generation low phase noise vco technology and can achieve 1ps or lower typical random rms phase jitter, easily meeting ethernet jitter requirements. the ics840004-01 is packaged in a small 20-pin tssop package. features ? four single-ended lvcmos/lvttl outputs 17 ? typical output impedance ? selectable crystal oscillator interface or single-ended input ? output frequency range: 56mhz - 175mhz ? vco range: 560mhz - 700mhz ? rms phase jitter at 156.25mhz (1.875mhz ? 20mhz): 0.52ps (typical) phase noise: offset noise power 100hz -94.9 dbc/hz 1khz -119.6 dbc/hz 10khz -128.9 dbc/hz 100khz -129.2 dbc/hz ? full 3.3v or mixed 3.3v core/2.5v output supply modes ? 0c to 70c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) packages frequency select function table for ethernet frequencies hiperclocks? ic s inputs output frequency (mhz), (25mhz reference) f_sel1 f_sel0 m div. value n div. value m/n ratio value 0 0 25 4 6.25 156.25 0 1 25 5 5 125 1 0 25 10 2.5 62.5 1 1 25 5 5 125 (default) 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 nc v dda npll_sel mr oe ref_clk nxtal_sel nc f_sel0 v dd f_sel1 gnd q0 q1 v ddo q2 q3 gnd xtal_in xtal_out osc phase detector vco m = 25 (fixed) f_sel1:0 0 0 4 0 1 5 1 0 10 1 1 5 (default) 0 1 1 0 2 n q0 q1 q2 q3 oe f_sel1:0 npll_sel nxtal_sel ref_clk mr xtal_in xtal_out pullup pulldown pulldown pulldown pulldown 25mhz pullup:pullup ics840004-01 20-lead tssop 6.5mm x 4.4mm x 0.925mm package body g package top view pin assignment block diagram
ics840004-01 femtoclocks? crystal-to-lvcmos/lvttl clock synthesizer idt? / ics? lvcmos/lvttl frequency synthesizer 2 ics840004ag-01 rev. b october 31, 2008 table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1, 20 f_sel0, f_sel1 input pullup frequency select pins. lvcmos/lvttl interface levels. 2, 9 nc unused no connect. 3 nxtal_sel input pulldown selects betweent he crystal or ref_clk inputs as the pll reference source. when high, selects ref_ clk. when low, selects xtal inputs. lvcmos/lvttl interface levels. 4 ref_clk input pulldown single-ended reference clock input. lvcmos/lvttl interface levels. 5 oe input pullup output enable pin. when high, the outputs are active. when low, the outputs are in a high impedance state. lvcmos/lvttl interface levels. 6 mr input pulldown active high master reset. when lo gic high, the internal dividers are reset causing the outputs to go low. when logic low, the internal dividers and the outputs are enabled. lvcmos/lvttl interface levels. 7 npll_sel input pulldown pll bypass. when low, the output is driven from the vco output. when high, the pll is bypassed and the output frequency = reference clock frequency/n output divider. lvcmos/lvttl interface levels. 8v dda power analog supply pin. 10 v dd power core supply pin. 11, 12 xtal_out, xtal_in input crystal oscillator interface. xtal_i n is the input. xtal_out is the output. 13, 19 gnd power power supply ground. 14, 15, 17, 18 q3, q2, q1, q0 output single-ended clock outputs. 17 ? typical output impedance. lvcmos/ lvttl interface levels. 16 v ddo power output supply pin. symbol parameter test conditions minimum typical maximum units c in input capacitance 4 pf c pd power dissipation capacitance 8 pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ? r out output impedance v ddo = 3.3v5% 17 ? v ddo = 2.5v5% 21 ?
ics840004-01 femtoclocks? crystal-to-lvcmos/lvttl clock synthesizer idt? / ics? lvcmos/lvttl frequency synthesizer 3 ics840004ag-01 rev. b october 31, 2008 absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 3a. power supply dc characteristics, v dd = 3.3v 5%, v ddo = 3.3v 5% or 2.5v 5%, t a = 0c to 70c table 3b. lvcmos/lvttl dc characteristics, v dd = 3.3v 5%, v ddo = 3.3v 5% or 2.5v 5%, t a = 0c to 70c note 1: outputs terminated with 50 ? to v ddo /2. see parameter measurement information section. load test circuit diagrams. item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, v o -0.5v to v ddo + 0.5v package thermal impedance, ja 73.2 c/w (0 lfpm) storage temperature, t stg -65 c to 150 c symbol parameter test conditio ns minimum typical maximum units v dd core supply voltage 3.135 3.3 3.465 v v dda analog supply voltage 3.135 3.3 3.465 v v ddo output supply voltage 3.135 3.3 3.465 v 2.375 2.5 2.625 v i dd power supply current 100 ma i dda analog supply current 12 ma i ddo output supply current 10 ma symbol parameter test conditions minimum typical maximum units v ih input high voltage v dd = 3.465v 2 v dd + 0.3 v v il input low voltage v dd = 3.465v -0.3 0.8 v i ih input high current nxtal_sel, npll_sel, ref_clk, mr v dd = v in = 3.465v 150 a oe, f_sel[0:1] v dd = v in = 3.465v 5 a i il input low current nxtal_sel, npll_sel, ref_clk, mr v dd = 3.465v, v in = 0v -5 a oe, f_sel[0:1] v dd = 3.465v, v in = 0v -150 a v oh output high voltage; note 1 v ddo = 3.3v 5% 2.6 v v ddo = 2.5v 5% 1.8 v v ol output low voltage; note 1 v ddo = 3.3v 5% or 2.5v 5% 0.5 v
ics840004-01 femtoclocks? crystal-to-lvcmos/lvttl clock synthesizer idt? / ics? lvcmos/lvttl frequency synthesizer 4 ics840004ag-01 rev. b october 31, 2008 table 4. crystal characteristics ac electrical characteristics table 5a. ac characteristics, v dd = v ddo = 3.3v 5%, t a = 0c to 70c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specification s after thermal equilibrium has been reached under these conditions. note 1: defined as skew between outputs at the same su pply voltage and with equal load conditions. measured at v ddo /2. note 2: this parameter is defined in accordance with jedec standard 65. note 3: please refer to the phase noise plots. parameter test conditions mi nimum typical maximum units mode of oscillation fundamental frequency 25 mhz equivalent series resistance (esr) 50 ? shunt capacitance 7pf drive level 1mw symbol parameter test conditions minimum typical maximum units f out output frequency f_sel[1:0] = 00 140 156.25 175 mhz f_sel[1:0] = 01 or 11 112 125 140 mhz f_sel[1:0] = 10 56 62.5 70 mhz t sk(o) output skew: note 1, 2 60 mhz tjit(?) rms phase jitter (random); note 3 156.25mhz, integration range: 1.875mhz ? 20mhz 0.52 ps 125mhz, integration range: 1.875mhz ? 20mhz 0.65 ps 62.5mhz, integration range: 1.875mhz ? 20mhz 0.55 ps t r / t f output rise/fall time 20% to 80% 200 700 ps odc output duty cycle f_sel[1:0] = 00, 01 or 11 43 57 % f_sel[1:0] = 10 49 51 %
ics840004-01 femtoclocks? crystal-to-lvcmos/lvttl clock synthesizer idt? / ics? lvcmos/lvttl frequency synthesizer 5 ics840004ag-01 rev. b october 31, 2008 table 5b. ac characteristics, v dd = 3.3v 5%, v ddo = 2.5v 5%, t a = 0c to 70c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specification s after thermal equilibrium has been reached under these conditions. note 1: defined as skew between outputs at the same su pply voltage and with equal load conditions. measured at v ddo /2. note 2: this parameter is defined in accordance with jedec standard 65. note 3: please refer to the phase noise plots. symbol parameter test conditio ns minimum typical maximum units f out output frequency f_sel[1:0] = 00 140 156.25 175 mhz f_sel[1:0] = 01 or 11 112 125 140 mhz f_sel[1:0] = 10 56 62.5 70 mhz t sk(o) output skew: note 1, 2 60 mhz tjit(?) rms phase jitter (random); note 3 156.25mhz, inte gration range: 1.875mhz ? 20mhz 0.48 ps 125mhz, integration range: 1.875mhz ? 20mhz 0.59 ps 62.5mhz, integration range: 1.875mhz ? 20mhz 0.53 ps t r / t f output rise/fall time 20% to 80% 200 700 ps odc output duty cycle f_sel[1:0] = 00, 01 or 11 43 57 % f_sel[1:0] = 10 49 51 %
ics840004-01 femtoclocks? crystal-to-lvcmos/lvttl clock synthesizer idt? / ics? lvcmos/lvttl frequency synthesizer 6 ics840004ag-01 rev. b october 31, 2008 typical phase noise at 62.5mhz (3.3v) typical phase noise at 62.5mhz (2.5v) 10gb ethernet filter phase noise result by adding a 10gb ethernet filter to raw data raw phase noise data ? ? ? 62.5mhz rms phase jitter (random) 1.875mhz to 20mhz = 0.55ps (typical) offset frequency (hz) noise power dbc hz 10gb ethernet filter phase noise result by adding a 10gb ethernet filter to raw data raw phase noise data ? ? ? 62.5mhz rms phase jitter (random) 1.875mhz to 20mhz = 0.53ps (typical) offset frequency (hz) noise power dbc hz
ics840004-01 femtoclocks? crystal-to-lvcmos/lvttl clock synthesizer idt? / ics? lvcmos/lvttl frequency synthesizer 7 ics840004ag-01 rev. b october 31, 2008 typical phase noise at 125mhz (3.3v) typical phase noise at 156.25mhz (3.3v) 10gb ethernet filter phase noise result by adding a 10gb ethernet filter to raw data raw phase noise data ? ? ? 125mhz rms phase jitter (random) 1.875mhz to 20mhz = 0.65ps (typical) offset frequency (hz) noise power dbc hz 10gb ethernet filter phase noise result by adding a 10gb ethernet filter to raw data raw phase noise data ? ? ? 156.25mhz rms phase jitter (random) 1.875mhz to 20mhz = 0.52ps (typical) offset frequency (hz) noise power dbc hz
ics840004-01 femtoclocks? crystal-to-lvcmos/lvttl clock synthesizer idt? / ics? lvcmos/lvttl frequency synthesizer 8 ics840004ag-01 rev. b october 31, 2008 parameter measureme nt information 3.3v core/3.3v lvcmos output load ac test circuit output skew output duty cycle pulse width/period 3.3v core/2.5v lvcmos output load ac test circuit rms phase jitter output rise/fall time scope qx lvcmos gnd v dd, 1.65v5% -1.65v5% v ddo v dda 1.65v5% t sk(o) v ddo 2 v ddo 2 qx qy t period t pw t period odc = v ddo 2 x 100% t pw q0:q3 scope qx gnd lvcmos v dd 1.25v5% -1.25v5% v ddo v dda 2.05v5% 2.05v5% phase noise mas k offset frequency f 1 f 2 phase noise plot rms jitter = area under the masked phase noise plot noise power 20% 80% 80% 20% t r t f q0:q3
ics840004-01 femtoclocks? crystal-to-lvcmos/lvttl clock synthesizer idt? / ics? lvcmos/lvttl frequency synthesizer 9 ics840004ag-01 rev. b october 31, 2008 application information recommendations for unused input and output pins inputs: crystal inputs for applications not requiring the use of the crystal oscillator input, both xtal_in and xtal_out can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from xtal_in to ground. ref_clk input for applications not requiring the us e of the reference clock, it can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from the ref_clk to ground. lvcmos control pins all control pins have internal pull-downs; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: lvcmos outputs all unused lvcmos outputs can be left floating . we recommend that there is no trace attached. power supply filtering technique as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter per- formance, power supply isolation is required. the ics840004-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v dd, v dda and v ddo should be individually connected to the power supply plane through vias, and 0.01f bypass capacitors should be used for each pin. figure 1 illustrates this for a generic v dd pin and also shows that v dda requires that an additional 10 ? resistor along with a 10 f bypass capacitor be connected to the v dda pin. figure 1. power supply filtering v dd v dda 3.3v 10 ? 10f .01f .01f
ics840004-01 femtoclocks? crystal-to-lvcmos/lvttl clock synthesizer idt? / ics? lvcmos/lvttl frequency synthesizer 10 ics840004ag-01 rev. b october 31, 2008 crystal input interface the ics840004-01 has been characterized with 18pf parallel resonant crystals. the ca pacitor values shown in figure 2 below were determined using a 25mhz, 18pf parallel resonant crystal and were chosen to minimize the ppm error. figure 2. crystal input interface lvcmos to xtal interface the xtal_in input can accept a single-ended lvcmos signal through an ac coupling capacitor. a general interface diagram is shown in figure 3. the xtal_out pin can be left floating. the input edge rate can be as slow as 10ns. for lvcmos inputs, it is recommended that the amplitude be re duced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. this configurat ion requires that the output impedance of the driver (ro) plus the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 ? applications, r1 and r2 can be 100 ? . this can also be accomplished by removing r1 and making r2 50 ? . figure 3. general diagram for lvcmos driver to xtal input interface xtal_in xtal_out x1 18pf parallel crystal c1 22p c2 22p xtal_in xtal_out ro rs zo = ro + rs 50 ? 0.1f r1 r2 v cc v cc
ics840004-01 femtoclocks? crystal-to-lvcmos/lvttl clock synthesizer idt? / ics? lvcmos/lvttl frequency synthesizer 11 ics840004ag-01 rev. b october 31, 2008 schematic example figure 4 shows a schematic example of the ics840004-01. an example of lvcmos termination is shown in this schematic. additional lvcmos termination approaches are shown in the lvcmos termination application note. in this example, an 18pf parallel resonant 25mhz crystal is used. the c1= 22pf and c2 = 22pf are recommended for frequency accuracy. for different board layouts, the c1 and c2 may be slightly adjusted for optimizing frequency accuracy. 1k ? pullup or pulldown resistors can be used for the logic control input pins. figure 4. p.c. ics840004-01 schematic example r5 100 ru1 1k zo = 50 ohm r4 100 r2 10 unused outputs can be left floating. there should be no trace attached to unused outputs. device characterized and specification limits set with all outputs terminated. vdd c3 10uf c1 22pf ru2 not install rd2 1k c6 0.1u xta l _ i n vdd if not using the crystal input, it can be left floating. for additional protection the xtal_in pin can be tied to ground. logic control input examples vddo vdd vdda x1 set logic input to '1' u1 ics840004_01 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 20 19 18 17 f_sel0 nc nxtal_sel ref_clk oe mr npll_sel vdda nc vdd xtal_out xta l _ i n gnd q3 q2 vddo f_sel1 gnd q0 q1 vdd to logic input pins lvcmos r3 36 rd1 not install c2 22pf vdd=3.3v vdd vddo=3.3v to logic input pins c5 0.1u optional termination zo = 50 ohm xta l _ o u t vdd c4 0.01u lvcmos set logic input to '0'
ics840004-01 femtoclocks? crystal-to-lvcmos/lvttl clock synthesizer idt? / ics? lvcmos/lvttl frequency synthesizer 12 ics840004ag-01 rev. b october 31, 2008 reliability information table 6. ja vs. air flow table for a 20 lead tssop transistor count the transistor count for ics840004-01: 3796 package outline and package dimensions package outline - g suffix for 20 lead tssop table 7. package dimensions for 20 lead tssop reference document: jedec publication 95, mo-153 ja by velocity linear feet per minute 0200500 single-layer pcb, jedec standard te st boards 114.5c/w 98.0c/w 88.0c/w multi-layer pcb, jedec standard test boards 73.2c/w 66.6c/w 63.5c/w note: most modern pcb designs use multi-layered boards . the data in the second row pertains to most designs. all dimensions in millimeters symbol minimum maximum n 20 a 1.20 a1 0.05 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 6.40 6.60 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.45 0.75 0 8 aaa 0.10
ics840004-01 femtoclocks? crystal-to-lvcmos/lvttl clock synthesizer idt? / ics? lvcmos/lvttl frequency synthesizer 13 ics840004ag-01 rev. b october 31, 2008 ordering information table 8. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 840004ag-01 ics840004a01 20 lead tssop tube 0 c to 70 c 840004AG-01T ics840004a01 20 lead tssop 2500 tape & reel 0 c to 70 c 840004ag-01lf ics40004a01l 20 lead ?lead-free? tssop tube 0 c to 70 c 840004ag-01lft ics40004a01l 20 lead ?l ead-free? tssop 2500 tape & reel 0 c to 70 c while the information presented herein has been checked for both a ccuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications, such as those requiring exte ded temperature ranges, high reliabilit y or other extraordinary environmental requirements are not recommended without additional processing by idt. idt rese rves the right to change any ci rcuitry or specifications with out notice. idt does not authorize or warrant any idt product for use in life support devi ces or critical medical instruments.
ics840004-01 femtoclocks? crystal-to-lvcmos/lvttl clock synthesizer idt? / ics? lvcmos/lvttl frequency synthesizer 14 ics840004ag-01 rev. b october 31, 2008 revision history sheet rev table page description of change date b t5a, t5b 4 - 5 ac characteristics tables - revi sed test conditions for output duty cycle. updated format throughout datasheet. 10/30/08
ics840004-01 femtoclocks? crystal-to-lvcmos/lvttl clock synthesizer www.idt.com ? 2008 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800-345-7015 (inside usa) +408-284-8200 (outside usa) contact information: www.idt.com

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